The main contribution of this research is defining a new mechanism to accurately measure the internal latencies between the hardware and software processes in a System-on-Chip Integrated Circuit. These heterogeneous platforms are the “heart” of the new intelligent equipment for the Energy Sector. However, to ensure its applicability in applications where real time operation is demanded it is necessary to know if the timing boundaries are fulfilled between all embedded subsystems. In the same SoC, it is feasible combining heterogeneous microprocessors, GPUs, peripheral, different Operating Systems running simultaneously and VHDL described IP cores for hardware acceleration. This research has been carried on in the context of the project HAZITEK ZE-2020/00022 founded by the by the Basque Government as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264; in both cases, they have been financed through the Fondo Europeo de Desarrollo Regional 2014-2020 (FEDER funds).