This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher.
Enhancing SoC on-chip bus security
Encryption AXI Transaction Core for Enhanced FPGA Security
A new contribution released in Open Access format by APERT reserach team
Lehenengo argitaratze data: 2022/10/18
(Beste leiho bat zabalduko du)The current hot topic in cyber-security is not constrained to software layers. As attacks on
electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible
with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.
Erreferentzia bibliografikoa
- Encryption AXI Transaction Core for Enhanced FPGA Security
- Electronics 2022, 11, 3361
- DOI: https://doi.org/10.3390/electronics11203361