The main objective of the project is the development of a configurable multi-feature hardware/software platform for driver assistance based on machine learning intellectual property (IP) cores. The architecture will be implemented using a programmable system-on-chip (PSoC) embedding ARM-Cortex cores and programmable logic. The programmable part of the PSoC (i.e. FPGA logic fabric) allows the implementation of several IP cores in a single chip, all of them performing DAS features in parallel. An immediate result of this project is, therefore, a reduction in the large amount of processing units that new cars embed. In addition, due to the versatility of machine learning algorithms and the multi-threading capability of FPGAs, the architecture will be flexible enough to cope with the incremental changes that new generations of vehicles are demanding. It will be able to adapt to the requirements of each level of driving automation, without changing the main architecture: this reduces costs and time to market, and enhances the vehicle reliability.