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Ph. D. Thesis

High-performance computing architecture for the Smart Grid

Doctoral student:
Le Sun
Year:
2024
Director(s):
Jesús Lázaro
Description:

With the rapid development of smart grid technology, the demand for high-performance computing (HPC) architectures to process large volumes of data has been increasing. This thesis presents an innovative high-performance computing architecture designed specifically for Sampled Values (SMV) processing in smart grids, with the aim of overcoming the limitations of CPU-based systems in complex data processing. By combining a custom-designed silicon IP and an FPGA-based accelerator board, this study offers an efficient solution using Xilinx's FPGA accelerator adaptive computing framework, significantly improving the speed and efficiency of data processing. Through experiments, we verify that the architecture can deploy multiple SV processing cores on a single FPGA accelerator, evaluating its performance in terms of data throughput, latency characteristics and system power consumption. The results indicate that this solution can satisfy the high speed, high throughput and low latency needs of smart grids. Furthermore, this thesis also explores the application of this architecture in smart grid fault detection and artificial intelligence inference, showing its potential and challenges to accelerate applications in smart grids. The contribution of this study is not only reflected in the provision of an efficient solution for data processing in smart grid communication infrastructure, but also supports the development of a centralized decision network architecture, boosting the application prospects of high-performance computing in the energy sector.


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