FPGAs (Field-Programmable Gate Arrays) and SoCs (Systems-on-chip) based on this technology, are electronic devices that can be configured in field, offering the possibility of developing a customized circuit in a short time-to-market with lower design costs than ASICs. Due to the continuous improvements on device performance, safety-oriented specific sectors such as automotive, railway, industrial, avionics aerospace and others, have shown interest in these devices. For these industries, the appliance of methods to estimate the system failure rate is mandatory, due to safety regulations. The problem lies in the fact that FPGAs are susceptible to radiation-induced SEUs (Single Event Upsets) in the configuration memory, a type of error that causes the random modification of one or more bits of this memory, affecting the implemented circuit. Therefore, reliability-oriented designs using commercial FPGAs must consider applying reliability mechanisms to mitigate SEUs. In addition to this, evaluation techniques are also necessary to corroborate the effectiveness of those strategies. Among the different applicable evaluation procedures, SEU emulation stands out. It consists of programming the device with an intentionally corrupted file, so that erroneous content is stored in the configuration memory, generating an effect analogous to SEU. Different emulation methodologies have been studied in the literature and a series of deficiencies have been observed. On the one hand, internal emulation methods (errors are injected from inside the FPGA itself) have the problem of being self-blocking, since the injected error can affect the emulation system itself. On the other hand, external emulation systems may require major changes at hardware level. The main objective of this thesis is the development of a SEU emulation mechanism able to be straightforwardly implemented in an already built system, whose unique requirement is containing a SoC FPGA such as Zynq or similar. Moreover, the proposed method intends to solve the deficiencies observed in the literature, taking advantage of the capacities offered by these SoCs. To this end, the error injection system has been proposed to be placed in the PS in order to prevent blocking injections. Although injections are made from outside the FPGA, they are carried out from inside the chip itself, avoiding the need of hardware modifications. A universal verification scheme has been proposed, so that the test can be adapted to different systems in a straightforward way. Once the emulation methodology has been described, two more contributions have been realised by this work. First, it has been analyzed the influence of different decisions taken during design process on the failure rate. Here, it has been proven that the failure rate in a concrete design can have fluctuations of up to 50% when some parameters are modified. On the other hand, having observed that the emulators of SEUs existing in the literature are focused on the study of SBUs (Single Bit Upsets), a procedure has been proposed for the estimation of the failure rate in the presence of MCUs (Multiple Cell Upsets).