The target of this step is to develop the digital logic hosted in the FPGA, i.e. the main element of the OEM_LLC module. This FPGA will support the Layer 1 (physical) and Layer 2 (link) of the communications towards the Ethernet side of the Gateway. When developing low level layers for communications on FPGAs, it is crucial that RTL-encoding be oriented to efficiently use the resources of the FPGA, and similarly to encode time-efficiently, i.e. that the low level circuit defined in VHDL can be synthesized even for high speeds.