Patent number 2379239. Published in B.O.P.I. in April 24th of 2011.

The present invention applies to the field of redundancy systems for correcting errors in digital circuits, and more specifically, to systems used in such voters. The voting circuit provides fast and reliable results since it is based on an arithmetic adder. The invention has 2n-1 input logic signals, n being an integer. The resulting output is at least one logic output indicating the value of the most repeated logic input signal. In order to do so an n bit adder is used. The adder’s inputs are the inputs to the logical system. In this way, the adder’s n output will provide the result of the voting process.