Patent number 2326718. Published in B.O.P.I. in October 16th of 2009.

This invention produces a continuously random signal synchronized with a high frequency square signal from an external oscillator. The random number sequence is of high entropy, that is to say, the correlation between bits close in time is nearly null. One Digital Phase Alignment Circuit (DPAC) generates the primary clock in phase with the oscillator. A specific control unit controls the phase delay in the output signal of a second DPAC in order to achieve a setup or hold timing violation in a flip-flop. The output of the flip-flop is unknown and the two logic states equally possible. It works in a metastable state.