The design of complex digital circuits, including a microprocessor, some peripherals and specific hardware, cannot be addressed by simply using powerful software tools. Neither traditional techniques nor intensive development times are enough. Only new strategies, focused more on the methodology than on resources, can take advantage from technologies that offer more than 100,000 logic gates per square millimeter. Among them: abstraction or top-down design, architecture exploration, predefined core integration, design based on platforms and hardware-software codesign. However, within the creation process of a complex system, the verification requires a special effort. As a matter of fact, it consumes most of the software and human resources; thus turning into the major challenge.

In the railway field, the electronics is becoming more and more relevant, compared with the mechanics. Nevertheless, suppliers, variety of products and scientific literature about railway electronic systems are scarce. The TCN (Train Communication Network) standard completely specifies all the levels in a local area network to interconnect both the devices inside a coach and the different carriages. This has been the European answer in telecommunications to railway manufacturers and operators.

In this thesis, some new electronic creation and verification techniques have been applied in order to design TCN devices. In fact, the master node architecture of the Multifunction Vehicle Bus (MVB) has been described following a codesign methodology, including some innovations. The ‘progressive device family’ concept has been crucial to determine which modules constitute the functional design. Subsequently, this architecture has been coded in the SystemC language. In this way, every block may be implemented either in hardware or in software. Finally, the Lee, Hsiung and Chen’s algorithm has guided the hardware-software partitioning.

In addition, a specific testbench to verify MVB devices has been created. On the basis of a commercial tool, it allows to perform effective simulations, configured by means of the user interface. Circuits under test and part of the environment must be described in VHDL. Nevertheless, the most complex tasks in the testbench have been programmed in C.