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System-on-Chip architecture for secure sub-microsecond synchronization systems

Doctoral student:
Naiara Moreira Ciruelos
Year:
2017
Director(s):
Armando Astarloa Cuellar
Description:

In this thesis, it is intended to address the problems associated with the cybernetic protection of the Precision Time Protocol (PTP). This is one of the most sensitive communication protocols among those considered by the standardization bodies for their application in future Smart Grids or smart electric networks. PTP's mission is to distribute a time reference from a master device to the rest of the slave devices, located within the same network, very precisely. The protocol is highly vulnerable, since introducing only a microsecond time error can cause serious problems in the protection functions of the electrical equipment, or even stop its operation.

For this, a new System-on-Chip architecture based on reconfigurable devices is proposed, with the aim of integrating the PTP protocol and the well-known MACsec security standard for Ethernet networks. The flexibility that modern reconfigurable devices provide has been exploited for the design of an architecture in which hardware and software processing coexist. The experimental results support the feasibility of using MACsec to protect the synchronization in industrial environments, without degrading the accuracy of the protocol.

Mention:
International PhD