This project addresses the design of a base SoC architecture based on the CPU architecture selected by the European Union for the design of integrated circuits in the future, RISC-V. This base SoC architecture will integrate communication mechanisms with industrial and artificial vision sensors, computing units for Artificial Intelligence and will incorporate security elements enabling functional safety certifications. The APERT Group of the UPV/EHU (project leader), CEIT, GAIA, Tekniker, Ikerlan and Ikor participate in the project.