Nowadays, the transistor density of electronic devices allows the integration of complete digital systems on a single integrated circuit. In order to reduce the development time and to face successfully these type of designs, they are made usually using cores. These cores, due to their complexity, often include processors inside. So, in these cases, they are called multi-processor systems.

This level of integration has also been spread to FPGA reconfigurable devices, which have been widely used because of their flexibility. In spite of that, the most common use of the reconfiguration capability is limited to the development stage of the design, to facilitate the debug process and, in some cases, to perform latter upgrades of the digital system.

However, the latest FPGAs allow to modify part of their configuration while the rest of the configured circuit remains running. This ability, called dynamic partial reconfiguration, has an additional interest in the designs that integrate digital systems on a single device. For these situations, the computations made into the chip can also set what context changes must be performed to the modules and apply them. These are the so called auto-reconfigurable systems.

Auto-reconfiguration is a complex operation. To perform it safely in a multi-processor core based system, the FPGA must both technologically admit the reconfiguration and contain a control system to manage the whole process.

This thesis proposes an auto-reconfiguration control system for multi-processor core based systems. First, a general proposal for the control system is presented. It is valid to be integrated into systems that use the most common standard specifications for System-on-a-Chip design. This generalization is described based on s generic multi-processor reconfigurable model, that is used to define the specifications of the different elements that build the control infrastructure. To help the designer to study the viability of the auto-reconfiguration in a design, the infrastructure area and time cost have been modeled and parameterized.

The proposed theoretic system is validated using a specific reconfigurable technology. For this purpose, all the elements specified in the control infrastructure are implemented, and some additional tools are developed to manage multi-processor and multi-context designs. The implemented infrastructure has been applied to three platforms that have been designed to experiment the auto-reconfiguration with the proposed approach. A custom prototype, that admits an exhaustive control of the FPGA configuration sequence, has been built to perform these experiments.